Q1 The binary equivalent of (1011·011)10
is equal to
[A] 11·375
[B] 10·123
[C] 11·175
[D] 9·234
Solution
1*2^3+0*2^2+1*2^1+1*2^0
=8+2+1=11
0*1/2+1*1/4+1*1/8=0.375
=11.375
Q2 The following switching functions
are to be implemented using a
decoder :
f1 = m (1, 2, 4, 8, 10, 14),
f2 = m (2,5, 9, 11),
f3 = m (2, 4, 5, 6, 7).
The minimum configuration of the
decoder will be
[A] 2 to 4 line
[B] 3 to 8 line
[C] 4 to 16 line
[D] 5 to 32 line
Solution
To implement functions using Decoder:
f1= Σ m( 1, 2, 4, 8, 10,14 ) Needs 16 minterms
f2 = Σ m( 2,5, 9,11) Needs 16 minterms
f3 = Σ m( 2,4,5,6,7) Needs 8 minterms
So therefore Option C 4 – to – 16 line Decoder
Q3 The parallel outputs of a counter
circuit represent the
[A] parallel data word
[B] clock frequency
[C] counter modulus
[D] clock count
Solution
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter counts the number of times an event takes place in accordance to the clock pulse.
Q4 In a k-way set associative cache,
the cache is divided into v sets,
each of which consists of k lines.
The lines of a set are placed in
sequence one after another. The
lines in set s are sequenced before
the lines in set (s+1). The main
memory blocks are numbered from
0 onwards. The main memory
block numbered j must be mapped
to any one of the cache lines from
[A] ( j mod v)* k to ( j mod v) * k+(k–1)
[B] ( j mod v) to ( j mod v) + (k–1)
[C] ( j mod k) to ( j mod k) + (v–1)
[D] ( j mod k) * v to ( j mod k) * v + (v–1)
Solution
Position of main memory set in the cache is = (Main memory block number) mod (Total number of cache sets)
As the lines in the set are placed in sequence, we can have the cache blocks (lines) from 0 to (k-1) in each set.
Number of sets = V, Main memory block number=J
So, 1st line of cache=
Last line of the cache=
Hence the correct answer is (j mod v) * k to (j mod v) * k + (k - 1).
Q5 Consider three different processors
P1, P2, P3 executing the same
instruction set. P1 has a 3 GHz
clock rate and a CPI of 1·5. P2 has
a 2·5 GHz clock rate and a CPI of
1·0. P3 has a 4 GHz clock rate and
a CPI of 2·2. If each processor
executes a program in 10 seconds,
find the number of instructions
executed by the processors.
[A] 18*10^3, 13*10^2, 17*10^5
[B] 20*10^9, 25*10^9, 18·18*10^9
[C] 18*10^4, 25*10^1, 20*10^3
[D] 3*10^1, 15*10^2, 2·5*10^3
Solution
No. Of instruction per second=processor speed/cpi
Each processor program in 10sec
P1=10*3.0*10^9/1.5
=20*10^9
P2=2.5*10^9*10/1.0
=25*10^9
P3=4.0*10^9*10/2.2
=18*10^9
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