Q2.Explain JK Flip flop advantage,disadvantage,applicationThis is the most common flip-flop among all. This simple flip-flop circuit has a set input (S) and a reset input (R). Apart from this, you can see the clock at the input end. At the output end, you will find two complementary outputs. The output is also feedback to the input visible in its circuit. Hence Q and Q’ are not the actual outputs. You can make this simple flip flop either using AND and NOR gates or just NAND gates. We have taken the basic circuit of SR flip flop using AND and NOR gates for better understanding. You can check the logic gate basics. Advantages There are several advantages to using an SR flip-flop. Some of them are listed below: Simplicity: The SR flip-flop is a simple and easy-to-understand circuit. Speed: The SR flip-flop is relatively fast, which makes it suitable for use in high-speed digital systems. Low power consumption: The SR flip-flop consumes very little power, which makes it suitable for use in battery-powered devices. Bi-stable operation: The SR flip-flop can be set and reset, making it a bi-stable circuit that can hold a state indefinitely until it is changed by an input signal. Limitations Apart from several advantages, there are some limitations associated with SR flip-flops. Some of them are listed below: Race condition:The SR flip-flop is susceptible to race conditions, which occur when the output state changes unpredictably due to variations in the timing of input signals. Invalid states: If both the set and reset inputs are activated at the same time, the SR flip-flop can enter an invalid state where both outputs are high or both are low. This can lead to unpredictable behavior in digital systems. Limited scalability: The SR flip-flop can be difficult to scale up to more complex digital systems, as it can lead to increased complexity and the potential for errors. Applications Some of the applications of SR flip-flop in real-world includes: Control systems: The SR flip-flop is used in control systems to synchronize signals and coordinate the operation of other components in the system. For example, in a traffic light control system. Memory storage: The SR flip-flop is used in memory storage devices such as registers, which are used to store data temporarily. Registers are used in a wide range of applications, including microprocessors, digital signal processors, and other digital circuits. Digital counters: The SR flip-flop can be used in digital counters to count up or down based on an input signal. For example, a timer circuit. Data synchronization: The SR flip-flop can be used to synchronize data signals between two digital circuits, ensuring that they are operating on the same clock cycle. This is useful in communication systems where data needs to be transmitted and received at specific times. Oscillators: The SR flip-flop can be used in conjunction with other components to create simple oscillators that generate a periodic signal. This is useful in applications such as clock circuits and audio signal generators. Truth table S R Q(N) 0 0 HOLD 0 1 0 1 0 1 1 1 Invalid Characterization table S R Q(N) Q(N+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 invalid 1 1 1 invalid Excitation table Q(n) Q(n+1) S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x 0
Q3.Explain T flip flop advantage,disadvantage,applicationJK Flip Flop is an improved version of SR flip flop where the undefined state of SR Flip Flop is eliminated by providing feedback. Let us take a look at the JK flip-flop logic diagram. We can make JK flip-flops using NAND gates only. But here we have taken a circuit that uses AND and NOR gates just like we discussed in SR flip flop. Advantages There are several advantages to using a JK flip-flop. Some of them are listed below: Toggle capability: It has a toggle capability, which means that it can be used to create a circuit that toggles between two states. No invalid states: Unlike the SR flip-flop, the JK flip-flop does not have any invalid states. Reduced race conditions: It is less susceptible to race conditions than the SR flip-flop, which can lead to more stable circuit operation. Bi-stable operation: Like the SR flip-flop, the JK flip-flop has a bi-stable operation, which means that it can hold a state indefinitely until it is changed by an input signal. Limitations Apart from several advantages, there are some limitations associated with JK flip-flops. Some of them are listed below: Complexity: The JK flip-flop is more complex than some other types of flip-flops, which can make it more difficult to design and implement in digital systems. Power consumption: The JK flip-flop can consume more power than other types of flip-flops, especially when used in toggle mode. Propagation delay: The JK flip-flop has a propagation delay, which can lead to timing issues in digital systems with tight timing constraints. Limited scalability: The JK flip-flop can be difficult to scale up to more complex digital systems, as it can lead to increased complexity and the potential for errors. Applications Some of the applications of JK flip-flop in real-world includes: Counters: The JK flip-flop can be used in conjunction with other digital logic gates to create a binary counter. This makes it useful in real-time applications such as timers and clocks. Data storage: The JK flip-flop can be used to store temporary data in digital systems. Synchronization: The JK flip-flop can be used to synchronize data signals between two digital circuits, ensuring that they are operating on the same clock cycle. This makes it useful in applications where timing is critical. Frequency division: The JK flip-flop can be used to create a frequency divider, which is a circuit that divides the frequency of an input signal by a fixed amount. This makes it useful in real-time applications such as audio and video processing.
Q4.Explain D flip flop advantage,disadvantage,applicationT flip flop is similar to JK flip flop. Just tie both J and K inputs together to get a T Flip flop. Just like the D flip flop, it has only one external input along with a clock. Advantages There are several advantages to using a T flip flop. Some of them are listed below: Single input: The T flip-flop has a single input that can be used to toggle between two states, which makes it simpler to use and easier to interface with other digital circuits. No invalid states: The T flip-flop does not have any invalid states, which helps to avoid unpredictable behavior in digital systems. Reduced power consumption: The T flip-flop consumes less power than other types of flip-flops, making it more energy-efficient. Bi-stable operation: Like other flip-flops, the T flip-flop has a bi-stable operation, which means that it can hold a state indefinitely until it is changed by an input signal. Easy to implement: The T flip-flop can be easily implemented using simple logic gates, which makes it a cost-effective option for digital systems. Limitations Apart from several advantages, there are some limitations associated with T flip-flops. Some of them are listed below: Inverted output: The output of a T flip-flop is inverted from the input, which can be confusing and make it difficult to design sequential logic circuits. Limited functionality: The T flip-flop can only store a single bit of information and cannot perform more complex operations like addition or multiplication. Glitches: The T flip-flop is vulnerable to glitches and noise on the input signal, which can cause it to toggle unexpectedly and lead to unpredictable behavior in digital systems. Propagation delay: Like other flip-flops, the T flip-flop has a propagation delay, which can lead to timing issues in digital systems with tight timing constraints. Applications Some of the applications of T flip flop in real-world includes: Frequency division: The T flip-flop can be used to divide the frequency of a clock signal by two, making it useful in applications such as digital clocks and frequency synthesizers. Frequency multiplication: The T flip-flop can also be used to multiply the frequency of a clock signal by two, making it useful in applications such as frequency synthesizers and digital signal processing. Data storage: The T flip-flop can be used to store a single bit of data, making it useful in applications such as shift registers and memory devices. Counters: The T flip-flop can be used in conjunction with other digital logic gates to create binary counters that can count up or down depending on the design. This makes them useful in real-time applications such as timers and clocks.
Q5Explain classification of binary codesD Flip flops or data flip flops or delay flip flops can be designed using SR flip flops by connecting a not gate in between S and R inputs and tying them together. D flip flops can be used in place of SR flip flops where you need only SET and RESET state. Advantages There are several advantages to using a D flip-flop. Some of them are listed below: Single input: The D flip-flop has a single data input, which makes it simpler to use and easier to interface with other digital circuits. No feedback loop: The D flip-flop does not have a feedback loop, which eliminates the possibility of a race condition and makes it more stable than other types of flip-flops. No invalid states: It does not have any weak states, which helps to avoid unpredictable behavior in digital systems. Reduced power consumption: The D flip-flop consumes less power than other types of flip-flops, making it more energy-efficient. Bi-stable operation: Like other flip-flops, the D flip-flop has a bi-stable operation, which means that it can hold a state indefinitely until it is changed by an input signal. Limitations Apart from several advantages, there are some limitations associated with D flip-flops. Some of them are listed below: No feedback: The D flip-flop does not have a feedback path, which means that it cannot be used for applications that require feedback control, such as servo systems or motor control. No toggling: It cannot be used for toggling applications since it only responds to the data input and not to the clock signal. Propagation delay: It has a propagation delay, which can lead to timing issues in digital systems with tight timing constraints. Limited scalability: The D flip-flop can be challenging to scale up to more complex digital systems, as it can lead to increased complexity and the potential for errors. Applications Some of the applications of D flip flop in real-world includes: Shift registers: D flip-flops can be cascaded together to create shift registers, which are used to store and shift data in digital systems. Shift registers are commonly used in serial communication protocols such as UART, SPI, and I2C. State machines: It can be used to implement state machines, which are used in digital systems to control sequences of events. State machines are commonly used in control systems, automotive applications, and industrial automation. Counters: It can be used in conjunction with other digital logic gates to create binary counters that can count up or down depending on the design. This makes them useful in real-time applications such as timers and clocks. Data storage: D flip-flops can be used to store temporary data in digital systems. They are often used in conjunction with other memory elements to create more complex storage systems.
Q6.Convert (242)10 into hexadecimal.Classification of binary codes The codes are broadly categorized into following four categories. Weighted Codes Non-Weighted Codes Binary Coded Decimal Code Alphanumeric Codes Error Detecting Codes Error Correcting Codes Weighted Codes Weighted binary codes are those binary codes which obey the positional weight principle. Each position of the number represents a specific weight. Several systems of the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits. Non-Weighted Codes In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes are Excess-3 code and Gray code. Excess-3 code The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as follows − Gray Code It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that, only one bit will change each time the decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation. Binary Coded Decimal (BCD) code In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express each of the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD. Alphanumeric codes A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But this is not enough for communication between two computers because there we need many more symbols for communication. These symbols are required to represent 26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols. The alphanumeric codes are the codes that represent numbers and alphabetic characters. Mostly such codes also represent other characters such as symbol and various instructions necessary for conveying information. An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e. total 36 items. The following three alphanumeric codes are very commonly used for the data representation. American Standard Code for Information Interchange (ASCII).
Q7Convert 0.52 into an octal number.242/16 remainder=2 quotient =15 15/16 remainder=15 quotient=0 so hexadecimal number is F2(f for 15)
Q8 Subtract (1101)2 and (1010)2.0.52*8=4.16 0.16*8=1.28 0.28*8=2.24 0.24*8=1.92 octal number is 4121
Q9Represent 5C6 in decimal.2s complement of 1010 is 0110 add 1101 and 0110 1101 0110 0011 Answer=0011
Q10Represent binary number 1.1 in decimal.5*16^2+12*16+6 =1678
Q11 Explain decoder1*(2)^0+1(1/2)^1 =1+0.5 =1.5
Q12 expain encoderA decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n -bit coded information has unused combinations, the decoder may have fewer than 2n outputs. The decoders presented here are called n -to- m -line decoders, where m … 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. Each combination of inputs will assert a unique output. The name decoder is also used in conjunction with other code converters, such as a BCD-to-seven-segment decoder. Consider the three-to-eight-line decoder circuit of three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables. The three inverters provide the complement of the inputs, and each one of the eight AND gates generates one of the minterms. The input variables represent a binary number, and the outputs represent the eight digits of a number in the octal number system. However, a three-to-eight-line decoder can be used for decoding any three-bit code to provide eight outputs, one for each element of the code. A two-to-four-line decoder with an enable input constructed with NAND gates is shown in Fig. The circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to 0 (i.e., active-low enable). As indicated by the truth table, only one output can be equal to 0 at any given time; all other outputs are equal to 1. The output whose value is equal to 0 represents the minterm selected by inputs A and B. The circuit is disabled when E is equal to 1, regardless of the values of the other two inputs. When the circuit is disabled, none of the outputs are equal to 0 and none of the minterms are selected. In general, a decoder may operate with complemented or un-complemented outputs. The enable input may be activated with a 0 or with a 1 signal. Some decoders have two or more enable inputs that must satisfy a given logic condition in order to enable the circuit. A decoder with enable input can function as a demultiplexer— a circuit that receives information from a single line and directs it to one of 2n possible output lines. The selection of a specific output is controlled by the bit combination of n selection lines. The decoder of Fig. can function as a one-to-four-line demultiplexer when E is taken as a data input line and A and B are taken as the selection inputs. The single input variable E has a path to all four outputs, but the input information is directed to only one of the output lines, as specified by the binary combination of the two selection lines A and B . This feature can be verified from the truth table of the circuit. For example, if the selection lines AB = 10, output D2 will be the same as the input value E, while all other outputs are maintained at 1. Since decoder and demultiplexer operations are obtained from the same circuit, a decoder with an enable input is referred to as a decoder – demultiplexer. A application of this decoder is binary-to-octal conversion.
Q13 Convert (111.101)2 to decimal.An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value. The above Encoder has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. It is assumed that only one input has a value of 1 at any given time. The encoder can be implemented with OR gates whose inputs are determined directly from the truth table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7. Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These conditions can be expressed by the following Boolean output functions: z = D1 + D3 + D5 + D7 y = D2 + D3 + D6 + D7 x = D4 + D5 + D6 + D7 The encoder can be implemented with three OR gates. The encoder defined above has the limitation that only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination. To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is encoded which is done in the Priority Encoder .
Q14 Convert octal(4057.06) to decimal(111.101)2 = (1 x4) + (1 x 2) + ( 1x1) + ( 1 x 0.5 ) + (0 x 0.25) + (1 x 0.125) = 4+ 2+ 1 + 0.5 + 0 + 0.125 = (7.625)10
Q15 explain boolean algebra.= 4 x 256 + 0 x 16 + 5 x 8 + 7 x 1 + 0 x 0.125 + 0.09375 = 2048 + 0 + 40 + 7 + 0 +0.0937 = (2095. 0937)10
Q16 what is idempotent law.Switching circuits are also called logic circuits, gates circuits and digital circuits. Switching algebra is also called Boolean algebra. Boolean algebra is a system of mathematical logic. It is an algebraic system consisting of the set of elements (0,1), two binary operators called OR and AND and unary operator called NOT. It is the basic mathematical tool in the analysis and synthesis of switching circuits. It is a way to express logic functions algebraically. Any complex logic can be expressed by a Boolean function. The Boolean algebra is governed by certain well developed rules and laws.
Q17 prove AB +A'C + BC = AB +A'C8. Idempotence Laws:- Idempotence means same value. Law 1: A. A = A Proof If A = 0, then A. A = 0. 0 =0 = A If A = 1, then A. A = 1. 1 = 1 = A This law states that AND of a variable with itself is equal to that variable only. Law 2: A + A = A Proof If A = 0, then A + A = 0 + 0 = 0 = A If A = 1, then A + A = 1 + 1 = 1 = A This law states that OR of a variable with itself is equal to that variable only.
Q18 explain dont care combinationAB +A'C + BC = AB +A'C Proof LHS = AB + A'C + BC = AB + A'C + BC (A+A') = AB + A'C + BCA + BCA' = AB (1 + C) + A'C (1+ B) =AB (1) +A'C (1) = AB + A'C = RHS
Q19 explain flip flop and latchThe combinations for which the values of the expression are not specified are called don’t care combinations or optional combinations and such expression stand incompletely specified. The output is a don’t care for these invalid combinations. The don’t care terms are denoted by d or X. During the process of designing using SOP maps, each don’t care is treated as 1 to reduce the map oth process of designing using POS maps, each don’t care is treated as 0 to reduce the map otherwise it is treated as 1 and left alone. A standard SOP expression with don’t cares can be converted into stand don’t cares as they are, and the missing minterms of the SOP form are written as the maxterms of the POS form. Similarly, to convert a standard POS expression with don’t cares can be converted into standard SOP form by keeping the don’t cares as they are, and the missing maxterms of the POS form are written as the minterms of the SOP form.
Q20 explain multiplexerFLIP-FLOP AND LATCH:- A flip-flop or latch is a circuit that has two stable states and can be used to store information. A flip-flop is a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-flop is either 0 or 1. Latch is a non-clocked flip-flop and it is the building block for the flip-flop. A storage element in digital circuit can maintain a binary state indefinitely until directed by an input signal to switch state. Storage element that operate with signal level are called latches and those operate with clock transition are called as flip-flops. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. A flip-flop is called so because its output either flips or flops meaning to switch back and forth. A flip-flop is also called a bi-stable multi-vibrator as it has two stable states. The input signals which command the flip-flop to change state are called excitations. Flip-flops are storage devices and can store 1 or 0. Flip-flops using the clock signal are called clocked flip-flops. Control signals are effective only if they are applied in synchronization with the clock signal. Clock-signals may be positive-edge triggered or negative-edge triggered. Positive-edge triggered flip-flops are those in which state transitions take place only at positive- going edge of the clock pulse.
Q21 what is the base r? (32)10=(44)RMULTIPLEXER:- A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected. A four-to-one-line multiplexer is shown in the below figure. Each of the four inputs, I0 through I3, is applied to one input of an AND gate. Selection lines S1 and S0 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one-line output. The function table lists the input that is passed to the output for each combination of the binary selection values. To demonstrate the operation of the circuit, consider the case when S1S0= 10. The AND gate associated with input I2 has two of its inputs equal to 1 and the third input connected to I2. The other three AND gates have at least one input equal to 0, which makes their outputs equal to 0. The output of the OR gate is now equal to the value of I2, providing a path from the selected input to the output. A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output line.
Q22 find base r? 12/2=332=4+4R 32-4=4R 28=4R R=7
Q23 Represent 5A6 in decimal12 in radix 10 2+R (2)R in radix 10 =2 (3)R in radix 10 =3 2+R/2=3 2+R=6 R=4
Q24 Convert 0.51 into an octal number.=5*16*16+10*16+6 =1446
Q25 Subtract (1101)2 and (1000)20.51*8=4.08 0.08*8=0.64 0.64*8=5.12 0.12*8=0.96 So octal number is 4050
Q26 Truth table of xor gate2s complement of 1000 first find 1s complement 0111 2's complement =0111+1=1000 1101 +1000 0101 After subrtraction result is 0101
Q27 Decode the ascii code. 1000010 1101001 1101100 1101100Truth table of xor gate a b a xor b 0 0 0 0 1 1 1 0 1 1 1 0
Q28 Truth table of half adder1000010 66 B 1101001 105 i 1101100 108 l 1101100 108 l so Bill is answer
Q29 find 10th complement of number 456a b sum carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
Q30 what are the possible base r for a number (254)R999 -456 543 10 th complement of number 456=543+1=544
Q31 what is the radix of the number if the solution of quadratic equation x^2-10x+31=0 is x=5radix=r digit= 0 to (r-1) highest value of digit in the number is 5 for digit 5 minimum radix or base should be 6.
Q32 find radius 25+60=115x^2-(10+0)x+10*3+1 x^2=(r+0)x+(3r+1)=0 put x=5 25-5r+3r+1 25-2r+1=0 -2r+26=0 r=13
Q33 Diff b/w synchronous and asynchronous counter5+2r+6r=5+r+r^2 5+8r=r^2+r+5 r^2-7r=0 r(r-7)=0 r=0,7
Q34 simplify using boolean expression f=abc+a'+ab'cA logic circuit is made up of a series of flip-flops that are used to count the number of inputs in the form of negative or positive edge transitions. The counter is classified into synchronous and asynchronous counters. The difference between the synchronous and asynchronous counter can be identified according to the flip-flops that are triggered. synchronus In the synchronous counter there are continuous clock input signals with flip-flops used to produce the output. In the synchronous counter, the operation is faster. Synchronous counter is also known as Parallel counter. Synchronous counter produces less error than asynchronous counter. Design of the Synchronous counter is complex. Synchronous counters can work with a flexible number of count sequences. Asynchronous In Asynchronous counters there are different clock signals used to produce the output. In Asynchronous counter the operation is slower. Asynchronous counter is also known as Serial counter. Asynchronous counter produces more errors than a synchronous counter. Design of the Asynchronous counter is simple. Asynchronous counters can work with a fixed number of count sequences.
Q35 Convert (101111010110.110110011)2 into octal.f=abc+a'+ab'c =abc+ab'c+a' =ac(b+b')+a' b+b'=1 according to boolean algebra law =ac+a' =(a+a')(c+a') a+a'=1 according to boolean algebra law. =c+a'
Q36 Convert (1011011011)2 into hexadecimalGroup of 3 bits are 101 111 010 110 . 110 110 011 Convert each group into octal = 5 7 2 6 . 6 6 3 The result is (5726.663)8
Q37 (4057.06) 8 to decimalGroup of 4 bits are 0010 1101 1011 Convert each group into hex = 2 D B The result is (2DB)16
Q38 Convert (A0F9.0EB)16 to decimal(4057.06) 8 = 4 x 8^3 + 0 x 8^2 + 5 x 8^1 + 7 x 8^0 + 0 x 8 ^–1 + 6 x 8^-2 = 2048 + 0 + 40 + 7 + 0 +0.0937 = (2095. 0937)10
Q39 Convert (B9F.AE)16 to octal.(A0F9.0EB)16 = (10 x 16^3 )+(0 x 16^2 )+(15 x 16^1 ) +( 9 x 16^0 ) +(0 x 16 ^– 1) +(14 x 16^- 2) +(11 x 16^-3) = 40960 + 0 + 240 + 9 + 0 +0.0546 + 0.0026 = (41209.0572)10
Q40 Add 679.6 from 536.8 using BCD addition.Given hexadecimal no.is B 9 F . A E Convert each hex. digit to binary = 1011 1001 1111 . 1010 1110 Group of 3 bits are = 101 110 011 111 . 101 011 100 Convert 3 bits group to octal. = 5 6 3 7 . 5 3 4 Result is (5637.534)8
Q41 Add 37 and 28 using XS-3 code.6 7 9 . 6 0110 0111 1001 . 0110 ( 679.6 in BCD) + 5 3 6 . 8 =>+ 0101 0011 0110 . 1000 (536.8 in BCD) 1 2 1 6 . 4 1011 1010 1111 . 1110 ( All are illegal codes) + 0110 +0110 +0110 .+0110 ( Add 0110 to each) 0001 0010 0001 0110 . 0100 1 2 1 6 . 4 ( corrected sum = 1216.4) Result is 1216.4
Q42 Convert the binary 1001 to the Gray code.3 7 0110 1010 ( 37 in XS-3) + 2 8 => + 0101 1011 ( 28 in XS-3) 6 5 1011 11010 ( Carry is generated) + 1 (propogate carry) 1100 0101 ( Add 0110 to correct 0101 and - 0011 +0011 subtract 0011 to correct 1100) 1001 1000 ( Corrected sum in XS-3 = 65)
Q43 Explain combination circuit1 xor 0=1 0 xor 0=0 0 xor 1=1 1st digit as it is write in gray code so gray code 1101
Q44 explain demultiplexerA combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. A combinational circuit performs an operation that can be specified logically by a set of Boolean functions. It consists of an interconnection of logic gates. Combinational logic gates react to the values of the signals at their inputs and produce the value of the output signal, transforming binary information from the given input data to a required output data. A block diagram of a combinational circuit is shown in the below figure. The n input binary variables come from an external source; the m output variables are produced by the internal combinational logic circuit and go to an external destination. Each input and output variable exists physically as an analog signal whose values are interpreted to be a binary signal that represents logic 1and logic 0
Q45 Truth,excitation,characteristic table of JK flip flop.The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the exact opposite of the Multiplexer. The demultiplexer takes one single input data line and then switches it to any one of a number of individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a parallel data at its output lines as shown below. The Boolean expression for this 1-to-4 demultiplexer above with outputs A to D and data select lines a, b is given as: F = (ab)’A + a’bB + ab’C + abD The function of the demultiplexer is to switch one common data input line to any one of the 4 output data lines A to D in our example above. As with the multiplexer the individual solid state switches are selected by the binary input address code on the output select pins “a” and “b” as shown
Q46 Truth,excitation,characteristic table of D flip flop.Truth table J K Q(n) 0 0 hold 0 1 0 1 0 1 1 1 toggle characteristic table of JK flip flop J K Q(n) Q(n+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 Excitation table of JK Q(n) Q(n+1) J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0
Q47 Truth,excitation,characteristic table of T flip flop.Truth table D Q(n) 0 0 1 1 characteristic table D Q(n) Q(n+1) 0 0 0 0 1 0 1 0 1 1 1 1 Excitation table Q(n) Q(n+1) D 0 0 0 0 1 1 1 0 0 1 1 1
Q48 (43.12)5=(?)10Tuth table T Q(n) 0 Q(n) 1 Q'(n) characteristic table T Q(n) Q(n+1) 0 0 0 0 1 1 1 0 1 1 1 0 Excitation table Q(n) Q(n+1) T 0 0 0 0 1 1 1 0 1 1 1 1
Q49 Truth table of SR Latch4*5^1+3*5^0+1*5^-1+2*5^-2 =23+7/25=(23.28)
Q50 Name of self complementary codeTruth table of SR latch S R Q(n) 0 0 invalid 0 1 1 1 0 0 1 1 hold
2421 code 3321 code 8421 code 6311 code excess-3 code Example 0 0000 1 0001 2 0010 3 0011 4 0100 5 1011 6 1100 7 1101 8 1110 9 1111 complement of 4=5 complement of 3=6 complement of 2=7 complement of 1=8 complement of 0=9 thats why 2421 is self complementary code.
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